1. Field of the Invention
This invention relates in general to the field of semiconductor device fabricating process, and more particularly to a method of fabricating a metal-oxide semiconductor (MOS) device suitable for using in the deep sub-micron process. The produced MOS device has elevated source/drain regions. Later, when performing a self-aligned silicidization process, the elevated source/drain regions are reacted to form a metal silicide. This can prevent ultra-shallow junction structure damage and thus improve product yield.
2. Description of Related Art
With the continuous progress in semiconductor manufacture technology, process precision has come into a so-called deep sub-micron era. In the deep sub-micron process, many device coefficients (such as the line width) are much smaller than that in prior art devices. Although utilizing electrical devices with smaller size provides the advantage of high integration, the manufacturing process itself is more difficult than ever. This invention is intended for a MOS transistor with shallow junction structure and provides a novel solution for preventing the shallow junction damage of a miniature device when performing a self-aligned silicidization process.
A shallow junction structure is mainly used in the source/drain regions of a MOS device. By forming shallow junction source/drain doped regions, lateral diffusion can be prevented and thus the properties of the MOS device are improved. As the process resolution increases, the source/drain regions of a MOS device are becoming even shallower. After completing the fabrication of a MOS device (wherein the gate electrode as well as the source/drain regions are fabricated), a self-aligned silicidization process is performed to form a metal silicide layer on the gate electrode and the source/drain regions, thus improving the junction characteristics between the device electrodes and the interconnects (i.e., reducing the contact resistivity). Such a self-aligned silicidization process, however, would probably cause the problem of shallow junction damage if a deep sub-micron process were conducted.
In a conventional self-aligned silicidization process, a metal layer, such as a titanium (Ti) layer, is sputtered on the device. By providing a high temperature, the metal layer is reacted with the silicon ingredient to form a metal silicide layer (e.g. titanium silicide, TiSi.sub.x). The un-reacted portion of the metal layer, such as that over the sidewall spacer of a gate electrode, is then removed. Thus, the desired metal silicide structure is achieved. As has been described above, not only the sputtered metal layer but also the silicon layers of the device are needed to execute the silicidization process. That is, a certain amount of silicon in the device is lost in the self-aligned silicidization process. For a shallow junction MOS device, it would consume too much intrinsic silicon in the source/drain regions and then cause damage to the shallow junction structure.
Regarding the above problem, most of the solutions currently in use intend to provide an additional silicon ingredient for the self-aligned silicidization process, thereby preventing the consumption of too much silicon in the source/drain regions. For example, after forming the electrodes of the semiconductor device (such as the gate electrode and the source/drain regions), a silicon implantation process is performed to provide additional silicon on the source/drain regions, or a selective epitaxial process is conducted to deposit additional silicon on the source/drain regions. Therefore, this additional silicon ingredient can be used to react with a metal layer to form the metal silicide layer without having to consume the intrinsic silicon of the source/drain regions.
However, since the solutions currently used are performed after finishing the semiconductor device fabrication, several problems occur. For example, the silicon implantation process not only adds the silicon ingredient to the source/drain regions, but also adds the silicon ingredient to other undesired areas, such as the sidewall spacer of the gate electrode. That is, the presence of the silicon ingredient outside the source/drain regions could cause a reaction with the metal layer to form a metal silicide layer, resulting in a short circuit problem. On the other hand, although the selective epitaxial process is able to form a silicon layer onto the desired area, a relatively high temperature of about 800.degree. C. to 1100.degree. C. is required. This would therefore raise the production cost and reduce the manufacturing efficiency.